Performance estimation in MPSoC design with SDF graphs

Multi-Processor Systems-on-Chip (MPSoC) are going to be the leading hardware platform featured in embedded systems, if they aren't already. This article deals with the performance estimation problem on these systems. Its purpose is the validation of a performance estimation methodology, proposed by the LIP2 laboratory (Tunis Faculty of Sciences, Tunis, Tunisia). Using the SDF3 tool, we modeled (1) a multimedia application using SDF graphs, (2) a target NoC-MPSoC platform, and (3) a performance constraint of 25 frames per second. With the same tool, we executed several static analyses to estimate the performances of the application (1) when ran on the target platform (2). Two approaches were adopted that are described in further details: graph transformation and processor specialization.