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Test Clock Domain Optimization to Avoid Scan Shift Failure Due to Flip-Flop Simultaneous Triggering

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8 Author(s)
Huang, Y.-C. ; Mentor Graphics Corporation, Hsinchu, Taiwan ; Tsai, M.-H. ; Ding, W.-S. ; Li, J.C.-M.
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This paper presents a design for testability technique to avoid scan shift failure due to flip–flop simultaneous triggering. The proposed technique changes test clock domains of flip–flops in the regions where severe IR-drop problems occur. A massive parallel algorithm using a graphic processor unit is adopted to speed up the IR-drop simulation during optimization. The experimental data on large benchmark circuits show that peak IR-drop values are reduced by 15% on average compared with the circuit after simple MD-SCAN partition. Our proposed technique quickly optimizes a half-million-gate design within two hours.

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:32 ,  Issue: 4 )

Date of Publication:

April 2013

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