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State-of-the-art TDCs can have a precision close to one picosecond, for which reason clock instability is starting to be one of the most significant factor limiting the precision. This paper provides methods to estimate clock jitter induced error by phase noise PSD measurements. Due to the different noise processes of the power-law model, convergence problems might restrict the time domain conversion of clock instabilities. Since time interval measurement corresponds to measuring the first difference of phase error, the convergence problems cannot be completely avoided as is usually done when characterizing frequency instabilities in time domain by measuring the 2nd differences of the phase error. This issue is addressed by taking into account the finite observation window of the phase error. Also a simple PSD measurement technique is introduced to provide an estimate of the jitter due to noise floor with an unknown bandwidth. Spurious tones in the phase noise PSD are also shown to have a significant impact on the precision of a TDC. The results are confirmed by several measurements done with a time-to-digital converter having a 1-ps precision.
Circuits and Systems I: Regular Papers, IEEE Transactions on (Volume:60 , Issue: 7 )
Date of Publication: July 2013