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Design low power 10T full adder using process and circuit techniques

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3 Author(s)
Mishra, Shipra ; Department of VLSI Design, ITM Universe Gwalior, M.P., India-474001 ; Tomar, Shelendra Singh ; Akashe, Shyam

In this paper we introduced 10T one-bit full adders, including the most motivating of those are analyzed and compared for speed, leakage power, and leakage current. The analysis has been performed on various process and circuits techniques, the analysis with minimum transistor size to minimize leakage power, the latter with simulate transistor dimension to minimize leakage current. The simulation has been carried out on a Cadence environment virtuoso tool using a 0.45 µm technology. Simulations have been also compared for different supply voltage values. Thus design guide-lines have been consequent to select the most suitable topology for the design features required. This paper also proposes a novel figure of merit to realistically compare n-bit adders implemented as a chain of one-bit full adders. The CMOS leakage current at the process level can be decreased by some implement on deep sub micron method. The circuit level technique reduces power consumption at very high level. In this paper we simulated the 10T Adder using many techniques both circuit level and process level.

Published in:

Intelligent Systems and Control (ISCO), 2013 7th International Conference on

Date of Conference:

4-5 Jan. 2013