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FPGA based implementation of a double precision IEEE floating-point adder

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3 Author(s)
Somsubhra Ghosh ; Dept. of Electrical Engineering, Jadavpur University, Kolkata, India ; Prarthana Bhattacharyya ; Arka Dutta

Floating-Point addition imposes a great challenge during implementation of complex algorithm in hard real-time due to the enormous computational burden associated with repeated calculations with high precision numbers. Moreover, at the hardware level, any basic addition or subtraction circuit has to incorporate the alignment of the significands. This paper presents a novel technique to implement a double precision IEEE floating-point adder that can complete the operation within two clock cycles. The proposed technique has exhibited improvement in the latency and also in the operational chip area management. The proposed double precision IEEE floating-point adder has been implemented with XC2V6000 and XC3S1500 Xilinx© FPGA devices.

Published in:

Intelligent Systems and Control (ISCO), 2013 7th International Conference on

Date of Conference:

4-5 Jan. 2013