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A Built-In Self-Repair Scheme for 3-D RAMs With Interdie Redundancy

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3 Author(s)
Che-Wei Chou ; Department of Electrical Engineering, National Central University, Taoyuan, Taiwan ; Yu-Jen Huang ; Jin-Fu Li

3-D integration using through silicon via is an emerging technology for integrated circuit designs. Random access memory (RAM) is one good candidate for the application of 3-D integration technology. However, yield will be a key challenge for the volume production of 3-D RAMs. In this paper, we present yield-enhancement techniques for 3-D RAMs. An interdie redundancy scheme is proposed to improve the yield of 3-D RAMs. Three stacking flows with respect to different bonding technologies for 3-D RAMs with interdie redundancy are proposed as well. Finally, a built-in self-repair (BISR) scheme is proposed to perform the repair of 3-D RAMs with interdie redundancies. The BISR circuits in two stacked dies can work together to allocate interdie redundancies. Simulation results show that the proposed yield-enhancement techniques can effectively improve the yield of 3-D RAMs.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:32 ,  Issue: 4 )