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With the constant decrease of semiconductor device dimensions, line edge roughness (LER) becomes one of the most important sources of device variability and needs to be controlled below 2 nm for the future technological nodes of the semiconductor roadmap. LER control at the nanometer scale requires accurate measurements. We introduce a technique for LER measurement based upon the atomic force microscope (AFM). In this technique, the sample is tilted at about 45° and feature sidewalls are scanned along their length with the AFM tip to obtain three-dimensional images. The small radius of curvature of the tip together with the low noise level of a laboratory AFM result in high resolution images. Half profiles and LER values on all the height of the sidewalls are extracted from the 3D images using a procedure that we developed. The influence of sample angle variations on the measurements is shown to be small. The technique is applied to the study of a full pattern transfer into a simplified gate stack. The images obtained are qualitatively consistent with cross-section scanning electron microscopy images and the average LER values agree with that obtained by critical dimension scanning electron microscopy. In addition to its high resolution, this technique presents several advantages such as the ability to image the foot of photoresist lines, complex multi-layer stacks regardless of the materials, and deep re-entrant profiles.