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We demonstrated lower power consumption of mobile CPU by replacing high-performance (HP)-SRAMs with spin transfer torque (STT)-MRAMs using perpendicular (p)-MTJ. The key points that enable the low power consumption are adapting run time power gating architecture (shown in Fig. 1), and satisfying both fast and low-power writing, namely, 3 nsec and 0.09 pJ, of p-MTJ cell (shown in Fig. 3). As shown in Table 1, only our developed p-MTJ has achieved 3 nsec, 0.09 pJ. Thanks to the fast and low-power p-MTJ, the power consumption of cache memory could be reduced by over 80% without degradation of performance.