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Novel hybrid DRAM/MRAM design for reducing power of high performance mobile CPU

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6 Author(s)
Abe, K. ; Corp. R&D center, Toshiba Corp., Kawasaki, Japan ; Noguchi, H. ; Kitagawa, E. ; Shimomura, N.
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This paper presents novel DRAM/MRAM hybrid memory design that enables effective power reduction for high performance mobile CPU. Power reduction by about 60% of SRAM-based cache while application is running can be achieved with D-MRAM-based cache memory in CPU. This result is attributable to both novel D-MRAM memory design and lowest programming energy, 0.09pJ, of advanced p-MTJ with ultra-high speed write and low power write (3ns, 50uA).

Published in:

Electron Devices Meeting (IEDM), 2012 IEEE International

Date of Conference:

10-13 Dec. 2012