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A QDR-Based 6-GB/s Parallel Transceiver With Current-Regulated Voltage-Mode Output Driver and Byte CDR for Memory Interface

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4 Author(s)
Seon-Kyoo Lee ; Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, Korea ; Byungsub Kim ; Hong-June Park ; Jae-Yoon Sim

This brief presents an 8-bit parallel transceiver for low-power memory interface with a current-regulated voltage-mode driver and a clock and data recovery performing both bit recovery and byte alignment. Sharing a current source by output drivers enables voltage swing control without any regulator circuit while holding the benefits of low-power voltage-mode driving. In the receiver, with only one phase rotator in a globally shared phase-locked loop, a narrow-range delay line in each deskewing phase recovery loop effectively performs seamless phase adjustment. The transceiver, implemented in a 90-nm CMOS, shows a data rate of 6 Gbit/s/ch with a bit error rate of 10-12 and a power consumption of 2.8 mW/Gbit/s.

Published in:

IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:60 ,  Issue: 2 )