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CMOS Imager With Focal-Plane Analog Image Compression Combining DPCM and VQ

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4 Author(s)
Oliveira, F.D.V.R. ; Electr. Eng. Program, Fed. Univ. of Rio de Janeiro, Rio de Janeiro, Brazil ; Haas, H.L. ; Gomes, J.G.R.C. ; Petraglia, A.

CMOS imagers, in comparison to CCD image sensors, have the great advantage of allowing for the implementation of signal processing circuitry inside the pixel matrix. We can extract information of interest from an image prior to analog-to-digital conversion. In this work, we present a 32 × 32 imaging integrated circuit that captures and compresses gray scale images on the focal plane of the image sensor using analog circuits that implement, for every 4 × 4 pixel block, differential pulse-code modulation, linear transform, and vector quantization. Theoretical details and circuit design are carefully described, as well as the test setup and details of the chip that was fabricated in a 0.35 μm CMOS technology. To validate the technique, we present tests and experimental results including overall modulation transfer function and photographs captured by the chip. The CMOS imager features focal-plane data compression based on DPCM and VQ with bit rate below 0.94 bpp and peak signal-to-noise ratio values around 18 dB. The overall power consumption is 37 mW (white image), which is equivalent to approximately 36 μW per pixel. Using photographs taken from bar-target pattern inputs, it is shown that details up to 2 cycles/cm are preserved in the decoded images.

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:60 ,  Issue: 5 )

Date of Publication:

May 2013

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