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A 0.6-V +4 dBm IIP3 LC Folded Cascode CMOS LNA With gm Linearization

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3 Author(s)
Yeo Myung Kim ; Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea ; Honggul Han ; Tae Wook Kim

This brief presents the design guidelines of LNAs under low-supply-voltage condition with respect to linearity and demonstrates an LNA that has excellent performance even with an extremely low supply voltage. Under a low supply voltage, the drain conductance nonlinearity, which can be ignored in a high supply voltage, is important, as well as the transconductance nonlinearity. Therefore, this brief linearizes transconductance using the multiple-gated transistor (MGTR) technique and tries to obtain high drain conductance linearity with the folded cascode configuration. The proposed 900-MHz LNA is designed with a 130-nm CMOS process. The measurement results show a gain of 15.4 dB, a noise figure of 1.74 dB, and an IIP3 of 4.09 dBm, which is the result of the 4.94-dB improvement over a conventional folded cascode LNA at 5.16-mW power consumption with a 0.6-V supply voltage.

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Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:60 ,  Issue: 3 )