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This letter presents an efficient multiternary digit (trit) adder design in carbon nanotube field effect transistor technology. The adder is based on an efficient single-trit full-adder design with low-complexity encoder and reduced complexity carry-generation unit. Further, we optimize the number of encoder and decoder blocks required while putting together several single-trit full-adder units to realize a multitrit adder. Extensive HSPICE simulation results show roughly 79% reduction in power-delay product for three-trit adders and 88 % reduction in power-delay product for nine-trit adders in comparison to a direct realization.