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A semidigital Gm-based amplifier is proposed for a low-power pipelined analog-to-digital converter (ADC). The amplifier performs a class-AB operation by smoothly changing between a comparator-like semidigital driver and a continuous-time high-gain amplifier according to the input voltage difference. A 10-bit pipelined ADC with 2.5-bit/stage architecture is implemented in a 0.13- CMOS. The ADC consumes 1.25 mW at a sampling rate of 25 MS/s and achieves a Nyquist-rate figure-of-merit of 139 and 232 fJ/c-s without and with power consumption from a resistor ladder, respectively.
Circuits and Systems II: Express Briefs, IEEE Transactions on (Volume:60 , Issue: 3 )
Date of Publication: March 2013