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3D integration using TSVs is a promising method to achieve further improvements for future electronic systems. When Copper TSVs are fabricated, Stress is induced in silicon near the TSV by CTE mismatch between filling copper and silicon substrate. For the substrate which has active circuits, the induced stress will influence the performance of the devices fabricated therein. To understand the impact of TSV induced stress on device performance deeply, this paper gives a comprehensive study. Orthotropic feature of silicon is considered to calculate the stress profile in silicon in vicinity of the Cu TSV. The saturation drain current variation of MOSFETs is calculated from the simulated stress data using the theory of piezoelectric effect. The results can well match the reported measuring data and show that it is an effective method to deeply understand the TSV induced stress and its impact on device performance.