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Low latency compute node architecture cooled by a two phase fluid flow

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9 Author(s)
Qidong Wang ; Key Lab. of Microelectron. Devices & Integrated Technol., Inst. of Microelectron., Beijing, China ; Guidotti, D. ; Lixi Wan ; Liqiang Cao
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As high performance multi-core scalar CPU and vector GPU processors approach 256 GFLOPSof processing power, transport latency and bandwidth (BW) between on-board DRAM and processor become a substantial bottleneck to optimal system performance. This is, in large part, because board level, data transport occurs over legacy L-C transmission lines having limited BW over a limited distance. As a consequence, high performance, systems running memory intensive applications are able to utilize only a fraction of their available computational potential and remain idle for many clock cycles while waiting for data and instructions. A number of alternate short range transport technologies are listed in the International Technology Roadmap for Semiconductors, among which the most promising is inter-chip optical communication. This paper proposes scalable, guided millimeter wave inter-chip communication with high speed I/Os on a common co-planar wiring net to reduce latency. Advantage is taken of high order digital M-QAM modulation to scale the spectral efficiency of carrier waves coding. Design advantage is offered by 3D DRAM stacking to achieve DRAM volume and 3D interposer stacking to achieve high I/O count and wiring escape BW. The compute module is designed to be enclosed and cooled by directhydrofluorocarbon jet spray or pool flow.

Published in:

Electronic Packaging Technology and High Density Packaging (ICEPT-HDP), 2012 13th International Conference on

Date of Conference:

13-16 Aug. 2012