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Process development of a stacked chip module with TSV interconnection

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9 Author(s)
Xiao Zhong ; National Key Laboratory of Science and Technology on Micro/Nano Fabrication, Peking University, Beijing, China ; Shenglin Ma ; Yunhui Zhu ; Yuan Bian
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In this paper, a novel 3D integration process named Via-Backside-Release process, abbreviated as VBR process, is proposed and technical issues are addressed. With VBR process, there's no need of removal process of copper overburden due to the filling of TSV by copper electroplating, and no individual unit process for producing Cu/Sn microbumps. In order to verify the feasibility of VBR process, a test run is carried out and a four-layer of chip module is demonstrated.

Published in:

Electronic Packaging Technology and High Density Packaging (ICEPT-HDP), 2012 13th International Conference on

Date of Conference:

13-16 Aug. 2012