Cart (Loading....) | Create Account
Close category search window

Bipolar process integration for a 0.25 μm BiCMOS SRAM technology using shallow trench isolation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

9 Author(s)
Tian, H. ; Adv. Products Res. & Dev. Lab., Motorola Inc., Austin, TX, USA ; Perera, A. ; Subramanian, C. ; Pham, D.
more authors

This paper describes bipolar process integration issues for a 0.25 μm BiCMOS SRAM technology which uses shallow trench isolation. In particular, we discuss: (1) minimization of arsenic buried layer induced surface step at the trench edge and its impact on gate poly bridging and bipolar collector to emitter leakage; (2) elimination of end of range damage from the selectively implanted collector (SIC) implant for improved bipolar current gain; and (3) optimization of the deep collector (sinker) implant for low resistance collector formation

Published in:

Bipolar/BiCMOS Circuits and Technology Meeting, 1997. Proceedings of the

Date of Conference:

28-30 Sep 1997

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.