Bipolar process integration for a 0.25 /spl mu/m BiCMOS SRAM technology using shallow trench isolation

This paper describes bipolar process integration issues for a 0.25 /spl mu/m BiCMOS SRAM technology which uses shallow trench isolation. In particular, we discuss: (1) minimization of arsenic buried layer induced surface step at the trench edge and its impact on gate poly bridging and bipolar collector to emitter leakage; (2) elimination of end of range damage from the selectively implanted collector (SIC) implant for improved bipolar current gain; and (3) optimization of the deep collector (sinker) implant for low resistance collector formation.