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Bipolar process integration for a 0.25 μm BiCMOS SRAM technology using shallow trench isolation

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9 Author(s)
Tian, H. ; Adv. Products Res. & Dev. Lab., Motorola Inc., Austin, TX, USA ; Perera, A. ; Subramanian, C. ; Pham, D.
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This paper describes bipolar process integration issues for a 0.25 μm BiCMOS SRAM technology which uses shallow trench isolation. In particular, we discuss: (1) minimization of arsenic buried layer induced surface step at the trench edge and its impact on gate poly bridging and bipolar collector to emitter leakage; (2) elimination of end of range damage from the selectively implanted collector (SIC) implant for improved bipolar current gain; and (3) optimization of the deep collector (sinker) implant for low resistance collector formation

Published in:

Bipolar/BiCMOS Circuits and Technology Meeting, 1997. Proceedings of the

Date of Conference:

28-30 Sep 1997

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