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Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes

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2 Author(s)
Cedric Walravens ; Dept. of Electr. Eng. (ESAT), KU Leuven, Leuven, Belgium ; Wim Dehaene

Radio communication exhibits the highest energy consumption in wireless sensor nodes. Given their limited energy supply from batteries or scavenging, these nodes must trade data communication for on-the-node computation. Currently, they are designed around off-the-shelf low-power microcontrollers. But by employing a more appropriate processing element, the energy consumption can be significantly reduced. This paper describes the design and implementation of the newly proposed folded-tree architecture for on-the-node data processing in wireless sensor networks, using parallel prefix operations and data locality in hardware. Measurements of the silicon implementation show an improvement of 10-20× in terms of energy as compared to traditional modern micro-controllers found in sensor nodes.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:22 ,  Issue: 2 )