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Tutorial T1B: Riding the "Energy Consumption Horse" - from System-level Design to Silicon

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Summary form only given. We begin with a survey of the system-level energy estimation techniques, with a look at the potential pitfalls and trade-offs in accuracy at various levels of modeling. We further discuss various approaches to estimate energy estimation accurately at higher abstraction levels. The main focus of the tutorial is on an energy estimation flow that has been successfully used in design of state-of-the-art Gigabit per second (Gbps), multi-stream Software Defined Radio (SDR) receiver supporting WLAN, LTE and DVB applications. The design flow itself is generic, and has been found immensely useful especially during energy optimization iterations. When a particular energy optimization was implemented at the back-end synthesis, we could percolate the benefits at higher abstraction levels and verify them for all the available applications to be run on the platform. Further, we show how our flow gave us quick and accurate feedback on performance figures with respect to feasibility of mapping a new upcoming wireless standard on our existing tape-out. The tutorial concludes with a look at some of the open problems in the area of system-level power modeling, both from a practical and research point of view.

Published in:

2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems

Date of Conference:

5-10 Jan. 2013