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Carbon Nanotube Field Effect Transistor (CNFET) has emerged as an alternative material to silicon for high performance, high stability and low power Static Random Access Memory (SRAM) design in recent years. SRAM functions as cache memory in computers and many portable devices. Therefore, CNFET based SRAM cell design is desired for low standby power cache memory. In CNFET based six transistor SRAM cell, access transistors contribute significantly to the leakage power during standby mode. This paper proposes a technique to reduce the standby power of SRAM by scaling the channel length of access transistor. An optimum channel length is selected using HSPICE simulation to ensure best performance in terms of stability, standby power and write time. The proposed design results in 37.2% and 40.6% improvements in standby power and static noise margin (SNM) respectively compared to the conventional CNFET SRAM cell with minimal write time trade off.