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Generally, image processing algorithms are suitable for parallel execution. However, this has not yet been exploited in a feasible design. Instead of the common practice, where the pixels on the sensor and the processor arrays are mapped onto each other, we propose the idea to split the image into multiple blocks of pixels (of the same size) and map each of these blocks onto one processing element. This decreases the hardware consumption and the communication overhead between the processing elements. This paper describes the architecture of the processor (the block-based image processor, BLIP) and the feasibility of low-, mid- and high-level image processing algorithms on the proposed architecture.