By Topic

A 24-GHz fully integrated phase-locked loop for 60-GHz beamforming

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Chunyuan Zhou ; Inst. of Microelectron., Tsinghua Univ., Beijing, China ; Lei Zhang ; Dongxu Yang ; Yan Wang
more authors

A 24-GHz fully integrated integer-N phase-locked loop (PLL) is presented in this paper. Benefiting from the bias noise filtering technique, the voltage controlled oscillator (VCO) in the loop achieves a low phase noise. Moreover, the supply voltage of VCO is as low as 0.8-V due to the low-threshold-voltage transistors used in the design. The proposed PLL is fabricated in 90-nm CMOS technology. The measurement results show that the PLL achieves a phase noise of -85dBc/Hz in band and -112dBc/Hz at 10-MHz offset from the carrier frequency of 24GHz. The whole chip occupies an area of 1.3 × 0.8mm2 and consumes 36-mW from a 1.2-V supply voltage (a 0.8-V supply voltage for VCO) excluding output driving buffers.

Published in:

Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on

Date of Conference:

Oct. 29 2012-Nov. 1 2012