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A secondary synchronization signal detection implementation for LTE downlink on a multi-core processor platform

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4 Author(s)
Xueqiu Yu ; State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China ; Maofei He ; Zhiyi Yu ; Xiaoyang Zeng

This paper presents an implementation for secondary synchronization signal (SSS) detection in LTE downlink based on a multi-core processor platform. In LTE initial cell search procedure, the SSS is used for cell-identity group detection and 10 ms frame timing. The multi-core processor platform is a mesh array consists of SIMD (Single Instruction Multiple Data) cores. Thanks to its programmability and reconfigurability, the multi-core processor platform is well suited for wireless communication applications. An implementation of SSS detection with the throughput of 105.9 Mbps is achieved by deeply excavating the task-level parallelism among several cores and mapping based on route-length-minimized principle, which shows the advantage of multi-core processor platform.

Published in:

Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on

Date of Conference:

Oct. 29 2012-Nov. 1 2012

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