A secondary synchronization signal detection implementation for LTE downlink on a multi-core processor platform

This paper presents an implementation for secondary synchronization signal (SSS) detection in LTE downlink based on a multi-core processor platform. In LTE initial cell search procedure, the SSS is used for cell-identity group detection and 10 ms frame timing. The multi-core processor platform is a mesh array consists of SIMD (Single Instruction Multiple Data) cores. Thanks to its programmability and reconfigurability, the multi-core processor platform is well suited for wireless communication applications. An implementation of SSS detection with the throughput of 105.9 Mbps is achieved by deeply excavating the task-level parallelism among several cores and mapping based on route-length-minimized principle, which shows the advantage of multi-core processor platform.