By Topic

Latchup I/O to I/O adjacency issues in peripheral I/O design for digital and analog applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Steven H. Voldman ; LLC, S. Burlington, Vermont 05403

CMOS latchup is a concern of standard cells in digital and analog design for peripheral I/O implementations. In this paper, I/O to I/O latchup analysis will be discussed. Test structures, and experimental results of I/O to I/O design issues will be shown. Interesting experimental effects have been observed and will be discussed for the first time.

Published in:

Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on

Date of Conference:

Oct. 29 2012-Nov. 1 2012