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A shuffle frog-leaping algorithm for test scheduling of 2D/3D SoC

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4 Author(s)
Xiao Le Cui ; Shenzhen Grad. Sch., Key Lab. of Integrated Microsyst., Peking Univ., Shenzhen, China ; Xin Ming Shi ; Hong Li ; Chung Len Lee

Test scheduling is an important issue for testing the SoC. This work proposes a modified shuffle frog-leaping algorithm for test scheduling to reduce the test application time under the peak power constraint. It is applied to the 2D as well as the 3D SoC and experimental results on benchmark circuits show that it is one of the most effective algorithms in solving the problem.

Published in:

Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on

Date of Conference:

Oct. 29 2012-Nov. 1 2012