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Wire sizing regulation algorithm for VLSI interconnect timing optimization

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4 Author(s)
Xin-Sheng Wang ; Sch. of Astronaut., Harbin Inst. of Technol., Harbin, China ; Liang Han ; Xing-Chun Liu ; Ming-Yan Yu

In this paper, we propose a Modified Active Set Algorithm (MASA) in optimal wire sizing problem for VLSI interconnect timing minimization. Based on the Elmore delay model, the optimal wire sizing can be formulated as a convex quadratic program, which is known to be solvable in polynomial time and derive an optimal solution. The algorithm is very efficient for arbitrary interconnect structures under the distributed Elmore delay model. The effectiveness of the algorithm is proved by the runtime compared with Active Set Algorithm.

Published in:

Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on

Date of Conference:

Oct. 29 2012-Nov. 1 2012