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A retiming based relaxation heuristic for resource-constrained loop pipelining

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2 Author(s)
V. Srinivasan ; Digital Design Environ. Lab., Cincinnati Univ., OH, USA ; R. Vemuri

This paper presents a fast and efficient heuristic for pipelining a loop under resource-constraints. The loop is represented as a dependence graph, G whose nodes are operations that are bound to available resources and edges denote the data dependencies between the operations. The data dependencies restrict the degree of parallelism that can be achieved while scheduling the graph. We propose a fast retiming based graph transformation technique which relates the data dependencies in the graph while maintaining functional equivalence. Relaxing data dependencies provides more flexibility for the scheduler to schedule operations, thereby leading to faster throughput. Our objective is to obtain a retimed graph which when scheduled achieves an optimal/near-optimal pipelined steady state throughput. A detailed algorithm is presented to solve the problem. We provide results that illustrate the effectiveness of our algorithm

Published in:

VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on

Date of Conference:

4-7 Jan 1998