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Speeding up program execution using reconfigurable hardware and a hardware function library

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4 Author(s)
S. Jain ; Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., New Delhi, India ; M. Balakrishnan ; A. Kumar ; S. Kumar

This paper describes a co-design environment which follows a new approach for speeding up compute intensive applications. The environment consists of three major components. First, a target architecture consisting of a uniprocessor host and a board with dynamically reconfigurable FPGAs and memory modules; second, a library of functions pre-synthesized for hardware or software implementation; and third, a tool which takes as input an application described in C and partitions it into hardware and software parts at functional granularity using information obtained by profiling the application. An important feature of the partitioning tool is a new efficient heuristic specifically suited for the architecture with reconfigurable hardware

Published in:

VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on

Date of Conference:

4-7 Jan 1998