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Fast arithmetic on Xilinx 5200 FPGA

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3 Author(s)
Laurent, B. ; Inst. Nat. Polytech. de Grenoble, France ; Bosco, G. ; Saucier, G.

In this paper, classical adder and multiplier architectures applied to the Xilinx XC5200 FPGA are compared. To inherit advantages of both structural and algorithmic approaches, hybrid solutions are proposed such that the optimal trade-off between architectures and technology is reached. The resulting schemes yield optimized performance after the use of Xilinx place and route tools

Published in:

VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on

Date of Conference:

4-7 Jan 1998

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