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Hybrid reconfigurable processors-the road to low-power consumption

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1 Author(s)
Rabaey, J.M. ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

Energy considerations are at the heart of important paradigm shifts in next-generation designs, especially in systems-on-a-chip era. With multimedia and communication functions becoming more and more prominent, coming up with low-power solutions for these signal-processing applications is a clear must. Harvard-style architectures, as used in traditional signal processors, incur a significant overhead in power dissipation. It is therefore worthwhile to explore novel and different architectures and to quantify their impact on energy efficiency. Recently, reconfigurable programmable engines have received a lot of attention. In this paper, the opportunity for substantial power reduction by using hybrid reconfigurable processors is explored. With the aid of a number of small benchmarks, it is demonstrated that power reductions of orders of magnitude are attainable

Published in:

VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on

Date of Conference:

4-7 Jan 1998