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A method for synchronizing IEEE 1149.1 test access port for chip level testability access

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1 Author(s)
D. Bhavsar ; Digital Equipment Corp., Hudson, MA, USA

This paper presents a novel method for using the industry standard IEEE Std. 1149.1 test port for accessing chip-wide testability features. The scheme reconfigures the test port to switch its normal asynchronous-to-chip-logic operating mode to a special synchronous-to-chip-logic operating mode that can be exploited in chip-alone test environments. The method allows the internal testability features to be designed normally and operated at full speed in chip's native clock domain

Published in:

VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on

Date of Conference:

4-7 Jan 1998