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Timing driven multi-FPGA board partitioning

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2 Author(s)
Burra, R. ; Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA ; Bhatia, D.

System level design is increasingly turning towards FPGAs to take advantage of their low cost and fast prototyping. In this paper we present a timing driven partitioning approach for an architecturally constrained multi-FPGA system. The partitioning approach uses path-based clustering based on the work by Dennis et al. (1995) and retiming. The board-level architecture is based on the PCB model consisting of four Xilinx 4013 FPGAs. The proposed algorithm has been tested on large scale real designs

Published in:

VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on

Date of Conference:

4-7 Jan 1998

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