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Improving area efficiency of FIR filters implemented using distributed arithmetic

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2 Author(s)
Sinha, A. ; Dept. of Electr. Eng., Indian Inst. of Technol., New Delhi, India ; Mehendale, M.

In this paper we present techniques for improving area efficiency of FIR filters implemented using the distributed arithmetic (DA) approach. These techniques exploit the flexibility in partitioning the filter coefficients for a two lookup-table (LUT) based DA implementation. The first technique is targeted at a ROM based implementation of LUTs and aims at minimizing number of columns/outputs of the ROMs. The second technique is targeted at a hardwired implementation of LUTs. We have developed an estimation technique for relative area comparisons of hardwired LUTs having the same number of inputs and outputs. We present a heuristic approach, based on this estimation technique, to optimally partition coefficients so as to achieve area-efficient hardwired implementation of LUTs. We present results to show these techniques can result in 10% to 15% area reduction for ROM based implementations and 20% to 25% area reduction for hardwired implementations

Published in:

VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on

Date of Conference:

4-7 Jan 1998

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