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Extensions to programmable DSP architectures for reduced power dissipation

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3 Author(s)
Mehendale, M. ; Texas Instrum. (India) Ltd., Bangalore, India ; Sherlekar, S.D. ; Venkatesh, G.

We present extensions to the programmable DSP architectures for reduced power dissipations. These extensions address power reduction in both external and internal buses, which form a major component of power dissipation in pipelined programmable processors such as DSPs. We present two techniques to reduce power dissipation in the program and data memory address buses, a technique to reduce cross-coupling related power dissipation in the program memory data bus and a technique for reducing power dissipation in the input buses of the ALU. We present results in terms of power savings using these techniques

Published in:

VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on

Date of Conference:

4-7 Jan 1998

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