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Coding for low-power address and data busses: a source-coding framework and applications

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3 Author(s)
S. Ramprasad ; Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA ; N. R. Shanbhag ; I. N. Hajj

Presented in this paper is a source-coding framework for the design of coding schemes to reduce transition activity. These schemes are suited for high capacitance busses where the extra power dissipation due to the encoder and the decoder circuitry is offset by the power savings at the bus. A framework to characterize low-power encoding schemes is developed based upon the source-channel coding view. In this framework, a data source (characterized in a probabilistic manner) is passed through a decorrelating function f1 first. Next, a variant of entropy coding function f2 is employed, which reduces the transition activity. The framework is then employed to derive novel encoding schemes whereby practical forms for f1 and f2 are proposed. Simulation results with an encoding scheme for data busses indicate an average reduction in transition activity of 36%. This translates into a reduction in total power dissipation for bus capacitances greater than 14 pF/bit in 1.2 μ CMOS technology and eight times more pourer savings compared to existing schemes with a typical value for bus capacitance of 50p F/bit. Simulation results with an encoding scheme for instruction address busses indicate an average reduction in transition activity by a factor of 3 times and 1.5 times over the Gray and TO coding schemes respectively

Published in:

VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on

Date of Conference:

4-7 Jan 1998