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A highly compact and tunable four-port power splitter was designed and fabricated in 180 nm CMOS process. Instead of distributed transmission lines, and LC lumped-element equivalent was selected for on-chip realization of the power splitter. To further reduce the varied by changing the bias current of the gyrator circuit. Experimental tests reveal that the power split is 6 dB and the center frequency can be tuned from 4.0 GHz to 5.5 GHz. The chip was biased from a 3 V dc voltage supply and consumes a maximum of 69 mW of power.