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Through-Silicon Via (TSV) is an emerging technology that enables vertical integration of silicon dies forming a single 3D-IC stack. In this paper, the electrical characteristics of coupling between TSVs and metal lines in 3D-ICs are analyzed. The simulation results for the electrical characteristics of the coupling between TSVs and metal lines in 3D-ICs show that the coupling is not negligible when TSV is relatively short compared to the TSV width, where the aspect ratio is less than 5. Therefore, TSV-to-wire capacitance needs to be considered for the computation of TSV capacitance. But, if the aspect ratio is larger than 5, the effect of metal wires is not considered. Moreover, the effect of metal lines on TSV-TSV coupling can be neglected if the pitch is less than 3x the TSV diameter.