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Logic synthesis of a PLL phase frequency detector

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2 Author(s)
Piguet, C. ; Centre Suisse d''Electronique et de Microtechnique SA, Neuchatel, Switzerland ; von Kaenel, V.

The design of the phase frequency detector of the phase-locked loop (PLL) of the Strongarm microprocessor has been designed according to an asynchronous design methodology based on negative gates. This methodology is based on a CMOS gate delay model which takes into account the delays of input inverters. The resulting phase frequency detector presents a better performance than the conventional circuits used generally in phase-locked loops

Published in:

Computers and Digital Techniques, IEE Proceedings -  (Volume:144 ,  Issue: 6 )