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Split-SAR ADCs: Improved Linearity With Power and Speed Optimization

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7 Author(s)
Yan Zhu ; State-Key-Lab. Analog & Mixed-Signal VLSI, Univ. of Macau, Macao, China ; Chi-Hang Chan ; U-Fat Chio ; Sai-Weng Sin
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This paper presents the linearity analysis of a successive approximation registers (SAR) analog-to-digital converters (ADC) with split DAC structure based on two switching methods: conventional charge-redistribution and Vcm-based switching. The static linearity performance, namely the integral nonlinearity and differential nonlinearity, as well as the parasitic effects of the split DAC, are analyzed hereunder. In addition, a code-randomized calibration technique is proposed to correct the conversion nonlinearity in the conventional SAR ADC, which is verified by behavioral simulations, as well as measured results. Performances of both switching methods are demonstrated in 90 nm CMOS. Measurement results of power, speed, and linearity clearly show the benefits of using Vcm-based switching.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:22 ,  Issue: 2 )