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A Low-Power Configurable Neural Recording System for Epileptic Seizure Detection

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4 Author(s)
Chengliang Qian ; Dept. of Electr. & Comput. Eng., Texas A&M Univ., College Station, TX, USA ; Shi, J. ; Parramon, J. ; Sanchez-Sinencio, E.

This paper describes a low-power configurable neural recording system capable of capturing and digitizing both neural action-potential (AP) and fast-ripple (FR) signals. It demonstrates the functionality of epileptic seizure detection through FR recording. This system features a fixed-gain, variable-bandwidth (BW) front-end circuit and a sigma-delta ADC with scalable bandwidth and power consumption. The ADC employs a 2nd-order single-bit sigma-delta modulator (SDM) followed by a low-power decimation filter. Direct impulse-response implementation of a sinc3 filter and 8-cycle data pipelining in an IIR filter are proposed for the decimation filter design to improve the power and area efficiency. In measurements, the front end exhibits 39.6-dB DC gain, 0.8 Hz to 5.2 kHz of BW, 5.86-μVrms input-referred noise, and 2.4-μW power consumption in AP mode, while showing 38.5-dB DC gain, 250 to 486 Hz of BW, 2.48-μVrms noise, and 4.5- μW power consumption in FR mode. The noise efficiency factor (NEF) is 2.93 and 7.6 for the AP and FR modes, respectively. At 77-dB dynamic range (DR), the ADC has a peak SNR and SNDR of 75.9 dB and 67 dB, respectively, while consuming 2.75-mW power in AP mode. It achieves 78-dB DR, 76.2-dB peak SNR, 73.2-dB peak SNDR, and 588-μW power consumption in FR mode. Both analog and digital power supply voltages are 2.8 V. The chip is fabricated in a standard 0.6-μm CMOS process. The die size is 11.25 mm2.

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Biomedical Circuits and Systems, IEEE Transactions on  (Volume:7 ,  Issue: 4 )