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Capped carbon hard mask and trimming process: A low-cost and efficient route to nanoscale devices

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4 Author(s)
Pauliac-Vaujour, Sebastien ; CEA, LETI, MINATEC Campus, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France ; Brianceau, Pierre ; Comboroure, Corinne ; Faynot, Olivier

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Both sub-22 nm architecture design optimization and reliable, low-cost process development represent major challenges toward nanoscale device fabrication. In order to address the second of these two issues, the authors have demonstrated that it is possible to overcome current tool and process lithography limitations using a capped carbon hard mask process, without dramatically increasing device fabrication costs, as only existing tools are used in this process. Starting from 50 nm patterns, 25 nm fully depleted silicon-on-insulator (FDSOI) transistors with good reliability and acceptable electrical behavior are obtained. This patterning solution may be applied to existing lithography processes (dry or immersion ArF lithography) in order to enhance current resolution capabilities. Moreover, the use of a capping layer enables to set free from photoresist thickness limitations, which are becoming increasingly critical for sub-22 nm feature patterning. Indeed, for such dimensions, photoresist thickness generally needs to be lower than 66 nm in order to avoid pattern collapse effects. This trend can lead to serious integration problems especially for the fabrication of thick stack device architectures. Therefore, in addition to improving current lithography processes, our strategy may also be useful for novel lithography processes such as extreme ultraviolet lithography or maskless lithography. The authors have also demonstrated that the capped carbon hard mask process could enable the patterning of sub-11 nm FDSOI gates, with a current best result close to 7 nm, starting from 30 nm photoresist patterns. Note that all etching steps of the process have been performed in the same etching chamber, which is a key point for meeting industrial requirements. These results show that it is possible to bypass tool and process lithography limitations to pattern sub-22 nm devices without dramatically increasing- fabrication costs while maintaining lithography throughput. The authors have therefore shown that the capped carbon hard mask process could be a high-performance and low-cost industry-compatible solution for nanoscale device fabrication.

Published in:

Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures  (Volume:31 ,  Issue: 2 )

Date of Publication:

Mar 2013

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