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As the technology continues to shrinks, leakage power is growing at exponential rate due to the aggressive scaling trends of channel lengths, gate oxide thickness, and doping profiles combined with an increasing number of transistors packaged in a single chip. During the physical implementation stages VLSI designs often needs be corrected due to the changes in specification or design rule constraints violations. This correction process is called Engineering Change Order (ECO). Spare cells are redundant cells introduced in the layout during early physical design stage whose inputs are traditionally tied to Power (VDD) or Ground (VSS) and will be used during ECO changes. However these spare or ECO cells in stand-by mode contributes to a significant subthreshold leakage power in lower technology nodes. In this paper we are proposing a method which involves assigning optimal standby at every input of spare cell gate based on state dependent leakage power tables to minimize leakage power of spare cells. The proposed method was tested on standard cell based LVDS layout created using Synopsys SAED 32/28nm and other available Synopsys Design Ware 65nm, 45nm, 40nm & 28nm standard cell libraries. With the proposed method we could observe 48% to 30% reduction in spare cell leakage power and 3.8% to 0.7% reduction in design leakage power.