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Path-based next trace prediction

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3 Author(s)
Jacobson, Q. ; Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA ; Rotenberg, E. ; Smith, J.E.

The trace cache is proposed as a mechanism for providing increased fetch bandwidth by allowing the processor to fetch across multiple branches in a single cycle. But to date predicting multiple branches per cycle has meant paying a penalty in prediction accuracy. We propose a next trace predictor that treats the traces as basic units and explicitly predicts sequences of traces. The predictor collects histories of trace sequences (paths) and makes predictions based on these histories. The basic predictor is enhanced to a hybrid configuration that reduces performance losses due to cold starts and aliasing in the prediction table. The Return History Stack is introduced to increase predictor performance by saving path history information across procedure call/returns. Overall, the predictor yields about a 26% reduction in misprediction rates when compared with the most aggressive previously proposed, multiple branch prediction methods

Published in:

Microarchitecture, 1997. Proceedings., Thirtieth Annual IEEE/ACM International Symposium on

Date of Conference:

1-3 Dec 1997