A new low-noise FET structure

A novel monolithic FET topology has demonstrated improved minimum noise figure when compared with a conventional pi-gate FET. The structure, referred to as the spider FET, has allowed noise figures to be achieved in monolithic LNA applications that are 0.3 dB lower than in the standard 0.5- mu m GaAs MESFET ion-implantation process. The improved spider FET performance is achieved by reducing the gate feed resistance and minimizing the parasitic gate-to-source capacitance in the region of the gate feed. The spider FET shows promise in 0.25- mu m MESFET and HEMT (high electron mobility transistor) applications, as well as in power FET applications.<
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