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Gate-level power and current simulation of CMOS integrated circuits

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4 Author(s)
A. Boliolo ; Dept. of Electr. & Comput. Eng., Bologna Univ., Italy ; L. Benini ; G. de Micheli ; B. Ricco

In this paper, we present a new gate-level approach to power and current simulation. We propose a symbolic model of complementary metal-oxide-semiconductor (CMOS) gates to capture the dependence of power consumption and current flows on input patterns and fan-in/fan-out conditions. Library elements are characterized and their models are used during event-driven logic simulation to provide power information and construct time-domain current waveforms. We provide both global and local pattern-dependent estimates of power consumption and current peaks (with accuracy of 6 and 10% from SPICE, respectively), while keeping performance comparable with traditional gate-level simulation with unit delay. We use VERILOG-XL as simulation engine to grant compatibility with design tools based on Verilog HDL. A Web-based user interface allows our simulator (PPP) to be accessed through the Internet using a standard web browser.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:5 ,  Issue: 4 )