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Instruction buffering to reduce power in processors for signal processing

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8 Author(s)
R. S. Bajwa ; Semicond. Res. Lab., Hitachi America Ltd., Brisbane, CA, USA ; M. Hiraki ; H. Kojima ; D. J. Gorny
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Power consumption analyzes of embedded processors indicate that a significant amount of power is consumed in accessing memory and in the control path. Based on this, and on the runtime characteristics of signal processing applications, we advocate the use of instruction buffering as a power-saving technique for processors for signal processing and multimedia applications. Two approaches, a decoded instruction buffer (DIB) and a decoded instruction cache, are considered. Performance improvements in representative applications in speech processing such as, the vector sum excited linear prediction (VSELP), linear prediction coding coefficient computation (LPC), and two-dimensional 2-D 8/spl times/8 DCT which is used in image compression, are provided. The reduction in power obtained is between between 25 and 30%.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:5 ,  Issue: 4 )