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In this paper, low-power Multi-Threshold MOS Current Mode Logic (MT-MCML) asynchronous pipeline circuits have been proposed. The circuits employ the use of multiple threshold MOS transistors to reduce the supply voltage requirement thereby decreasing their power consumption. The proposed circuits have been implemented and simulated in PSPICE using 0.18 μm CMOS technology parameters. Their performance with the conventional MCML circuits indicates that the proposed circuits consume less power than the conventional ones.
Date of Conference: 6-8 Dec. 2012