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Graphical visualisation, Electronic Design Automation (EDA) tools and reuse of intellectual property are established methods for increasing the speed and productivity of FPGA system design. Many commercial EDA products for FPGA development use graphical visualisation of Hardware Description Language (HDL) code to assist engineers. However, these tools usually don't abstraction clock or bus signals. Furthermore, reuse of HDL modules tends to involve much time spent connecting a range of commonly understood connectors for the module to work; automating these connection tasks could save time and simplify designs. This paper presents a model-based rapid prototyping tool for use in SDR on a reconfigurable computing platform. The tool will facilitate a novice developer or researcher to develop and experiment with SDR processing applications deployed on a FPGA platform. A prototype version of this tool, which integrates with Xilinx EDK, is presented in this paper together with results of testing the tool by implementing an example FM receiver chain.