Cart (Loading....) | Create Account
Close category search window
 

Concurrent error detection in nonlinear digital circuits using time-freeze linearization

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Chatterjee, A. ; Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA ; Roy, R.K.

Concurrent error detection in digital circuits is very important in applications where error in processed data can have catastrophic effects. Typically, error detection is performed by a small amount of additional hardware called the checking circuit. In the past, researchers have developed techniques for concurrent error detection in linear digital state variable circuits. In this paper, we investigate concurrent error detection techniques for nonlinear digital circuits that compute polynomial functions of multiple variables. Such circuits have widespread use in the design of various classes of nonlinear digital filters. The proposed error detection schemes are possible due to the use of a new linearization method called time-freeze linearization. In this method, a nonlinear circuit is modeled as a linear circuit for each individual time frame corresponding to the time taken to process a given set of input data. The defining parameters of this linear model change from one time frame to another but are regarded as fixed or frozen in any given time frame. This allows the use of real number checksum codes for fault detection. As opposed to duplicating the entire nonlinear part of the circuit, our approach allows us to use the nonlinear functions to drive the check circuitry, while achieving full fault coverage at low hardware cost

Published in:

Computers, IEEE Transactions on  (Volume:46 ,  Issue: 11 )

Date of Publication:

Nov 1997

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.